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BBN TC2000

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Overview

Introduced in August 1989.

The TC2000 was the first large-scale implementation of a RISC architecture in the late eighties. It was targeted towards real-time simulation, industrial process control, decision support, on-line database management, and project planning and control. It was a scalable shared-memory multi-processor architecture The TC2000 allowed expansion of the base system from eight to 128 CPUs, with each CPU sitting on a designated processor board. The architectural limit was 512 CPUs, though there weren't any system delivered in that size.

• 25MHz 88100 CPU
• 3 88200 CMMUs
• 16KB/16KB external L1 I/D cache
• 16MB local RAM
• VMEbus interface
• Function cards communicate and share memory via BBN's proprietary Butterfly network switch interconnect.
• Latency for accessing other CPU-cards memory was substantially greater (15:1) than for local RAM.

The price for a base model was in 1989 was $350,000; BBN stopped selling these systems in 1991.

Maximum theoretical system capabilities were, for 504 processors:

• Integer - 9,576 MIPS based on Dhrystones
• Whetstone - 6,552 megaWhetstones
• Floating point - 10,080 MFLOPS
• Memory - 16,096 MBytes
• I/O Bandwidth - 2,560 MBytes/sec

Operating Systems

• At the beginning used a proprietary OS, called Chrysalis
• pSOS+m, a real-time executive
• nX, based on Unix 4.3BSD and Mach

References:

• Bolt, Beranek and Newman (BBN) TC2000 (Survey of High Performance Computing Systems, 1999, from Northeast Parallel Architectures Center (NPAC) at Syracuse University)
• Bolt, Beranek and Newman Advanced Computers Inc. Time Critical 2000 (Tom Uban)

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